Method and structure for manufacturing improved yield semiconductor packaged devices

ABSTRACT

A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.

TECHNICAL FIELD

[0001] The present invention relates to semiconductor packaging, andmore particularly, to attaching a semiconductor die in a device package.

BACKGROUND OF THE INVENTION

[0002] Semiconductor devices are typically fabricated on thin wafers ofsilicon. Several dice are produced on each wafer, with each dierepresenting a single semiconductor device. Each die on a wafer istested for gross functionality, and sorted according to whether the diepasses or fails the gross functionality test. After being sortedaccording to gross functionality, the wafers are cut using a wafer saw,and the individual die are singulated. The die determined to benon-functional are scrapped. The functional die are packaged and furthertested to ensure that each packaged device satisfies a minimum level ofperformance. Typically, the functional devices are permanently packagedby encapsulating the die in a plastic package. Packaging of thefunctional devices facilitates handling of the devices and also protectsthe die from damage during the manufacture of circuits using thepackaged devices.

[0003] There are several conventional structures and methods forpackaging singulated die. For example, more common package types includesmall outline j-bend (SOJ) packages, thin small outline packages (TSOP),and zigzag in-line packages (ZIP). The finished packaged devices areoften mounted onto a substrate to form a module. A singulated die ispackaged in the aforementioned package types by attaching the die to alead frame paddle and electrically coupling exposed bond pads of the dieto metal leads. The lead frame, die, and a portion of the metal leadsare subsequently encapsulated by a plastic resin to protect theintegrated circuit from damage. The encapsulated device is then trimmedfrom the lead frame and the metal leads formed to the correct shape.

[0004] An alternative lead frame structure, known as lead on chip (LOC)may be employed instead of the structure having a lead frame paddle. Inan LOC structure, individual metal leads are typically attached to thesurface of the die using double-sided adhesive tape having a polyimidebase coated on both sides with adhesive material. The metal leads anddie are then heated to attach to the adhesive material. The bond pads ofthe semiconductor die are subsequently wire bonded to a respective metallead to electrically connect the semiconductor die to receive electricalsignals applied to the conductive leads. The LOC lead frame and die arethen encapsulated in a plastic resin, then followed by a trim and formprocess. The LOC structure and packaging process are described in U.S.Pat. No. 4,862,245 to Pashby et al., issued Aug. 29, 1989, and U.S. Pat.No. 4,916,519 to Ward, issued Apr. 10, 1990, which are incorporatedherein by reference.

[0005] Recently, semiconductor manufacturers have developed a packagestructure where unpackaged die are mounted directly onto a substrate,for example, a printed circuit board, thus allowing modules to bedesigned with increased device density. Examples of these types ofpackages structures include ball grid array (BGA) packages, and otherchip scale packages (CSP) having package dimensions that are slightlylarger than the dimension of the encapsulated die. The die is mountedonto the substrate and is electrically coupled to conductive tracesformed on the substrate by wire bonding the bond pads of the die.Alternatively, the conductive traces and the bond pads may beelectrically coupled by using tape automated bonded (TAB) wire instead.The resulting structure is subsequently, partially or entirely,encapsulated to protect the device from damage. External leads, often inthe form of solder balls, are then attached to attachment sites on theconductive traces so that the integrated circuit fabricated on the diemay be electrically contacted through the external leads.

[0006] Following packaging, the device is typically mounted onto aprinted circuit board (PCB) as a component in a larger electronicsystem. Conductive pads on the PCB are positioned to correspond to thelocation of the external leads of the packaged device. The packageddevice is positioned accordingly onto the conductive pads and subjectedto a reflow process at an elevated temperature in order to solder thepackaged device to the PCB. In the case of a BGA type package, thesolder is provided by the solder balls of the completed package.

[0007] After the solder has cooled, the packaged device is rigidlyattached to the PCB. However, there may be an issue with regards to thereliability of the solder joints as a result of the different expansionrates of the semiconductor die of the packaged device and the PCB towhich the packaged device is soldered. The coefficient of thermalexpansion (CTE) of the die is typically much lower than that for thePCB. Thus, when the electronic system reaches its operating temperature,the PCB will expand more than the die. The thermal mismatch results in ashearing stress focused at the interface between the packaged device andthe PCB, namely, the solder joints. The reliability of the electronicsystem is compromised when the thermal mismatch stress applied to thesolder joints of the packaged device is great enough to cause one of thesolder joints to fail.

[0008] One method that has been used to alleviate some of the thermalmismatch stress at the solder joint is using a package structure wherethe die is attached to a flexible substrate using a compliant elastomerpad. Upon reaching operating temperature, the PCB will expand andlaterally shift the position of the contact pads with respect to thedie. The compliant nature of the elastomer pad allows the solder ballsof the packaged device to shift laterally with the expanding PCB. Thus,the different expansion rates of the die in the packaged device, and thePCB to which the packaged device is soldered, is accommodated by theflexible elastomer pad attaching the die to the flexible substrate.However, in the case where TAB wire connections are used in such apackage structure to electrically couple the bond pads of the die to theconductive traces of the substrate, thermal expansion of the elastomerpad creates reliability problems for the packaged device itself. It hasbeen shown in reliability testing that the TAB wire joint is the pointmost susceptible to failure when the packaged device is subjected totemperature cycle tests (e.g., −65° C. to +150° C.) or high temperatureand humidity tests (e.g., 85° C., 85% RH, alternating bias). Thermalexpansion of the elastomer pad laterally shifts the position of theflexible substrate relative to the bond pads of the die. Consequently,the resulting compliant structure places stress at the TAB wire jointwhere the wire is bonded to the bond pad of the die.

[0009] Another method that has been used to minimize thermal mismatchstress between the die and the PCB is to attach the die to a flexiblesubstrate with elastomer posts. One example of this type package is aproduct developed by Tessera called μBGA®. Viscous elastomer material isscreen printed onto the flexible substrate and cured to form theelastomer posts. A dry or wet die attach adhesive is then applied to theend of the cured elastomer in order to attach the die to the elastomerposts. Subsequently, the bond pads of the die are electrically coupledto the conductive traces of the flexible substrate by a TAB wiringprocess. Although the resulting compliant structure accommodates thedifferent expansion rates of the die and the PCB, the assembly processis time-consuming. Additional assembly steps are required to screenprint the viscous elastomer material onto the flexible substrate, tocure the viscous material, and to apply the dry adhesive to theresulting elastomer post. As a result, product throughput at theassembly stage is reduced.

[0010] Furthermore, attaching the die to the substrate using elastomerposts requires precision processing to maintain assembly yields. Intypical CSP type packages, coplanarity of the die and the substrateshould be maintained to ensure that all solder balls contact the PCBupon reflow. Thus, the height of the elastomer posts should besubstantially the same in order to achieve the required coplanarity.However, precision processing and equipment is required to achieve thislevel of consistency. Variations in the screen printing process or inthe attachment of dry adhesive to the elastomer posts may result inunacceptable coplanarity, and consequently, unacceptable packageddevices.

[0011] Therefore, there is the need for a method and structure for asemiconductor package that can alleviate thermal mismatch stress withoutcompromising the reliability of the package structure or adding severaladditional process steps.

SUMMARY OF THE INVENTION

[0012] The present invention is directed to a high reliabilitysemiconductor package structure. The package structure is a ball gridarray type package that uses a plurality of pieces of adhesive film toattach a semiconductor die to a substrate having conductive traces inorder to alleviate thermal mismatch stress between the semiconductor dieand the printed circuit board to which the packaged device is soldered,while maintaining the reliability of the packaged device itself.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIGS. 1A-B is an isometric view of a semiconductor packagestructure according to an embodiment of the present invention.

[0014] FIGS. 2A-B is a cross-sectional view of alternative embodimentsof the semiconductor package structure shown in FIG. 1.

[0015] FIGS. 3A-B is a cross-sectional view of the semiconductor packagestructure shown in FIG. 1 and a conventional semiconductor packagestructure

DETAILED DESCRIPTION OF THE INVENTION

[0016] Embodiments of the present invention use a plurality of pieces ofadhesive film to attach a semiconductor die to a substrate in a BGA typepackage. Using multiple pieces of adhesive film alleviates some of thethermal mismatch stress between the semiconductor die and the PCB towhich the packaged device is soldered, while maintaining the reliabilityof the packaged device itself. As will be illustrated below, the sumchange in the length of the pieces of adhesive film will be less thanthe change in the length of a elastomer pad of a conventional BGApackage structure of similar size. Thus, the stress applied to the TABwire joints caused by thermal expansion will be reduced with respect tothe conventional package structure. The pieces of adhesive film areattached to the substrate by pressure bonding, and the die issubsequently pressure bonded to the opposite surface of the pieces ofadhesive film. Coplanarity of the die and the substrate is maintained bythe substantially uniform thickness of the pieces of adhesive film.

[0017] Shown in FIGS. 1 and 2 is a BGA type package structure 10according to an embodiment of the present invention. A semiconductor die12 having an integrated circuit (not shown) and conductive bond pads 14fabricated on a surface of the die 12 is attached to a substrate 16. Thesubstrate 16 has conductive traces 18, or interconnects, to which thebond pads 14 are coupled. The substrate 16 may be a rigid organicsubstrate, such as BT resin, or FR-4 or FR-5 material, or a flexiblesubstrate, such as polyimide. A person of ordinary skill in the art willappreciate that the substrate 16 may formed from materials other thanthose described herein. Consequently, the type of material used for thesubstrate 16 does not limit the scope of the present invention.

[0018] External terminals 20, typically in the form of solder balls,will be formed on the opposite side of the substrate 16 and coupled to arespective conductive trace after the package structure 10 isencapsulated to protect the die 12 and substrate 16 from damage. Thesubstrate 16 serves as an interposer coupling the bond pads 14 of thedie 12 attached to one side to the external terminals 20 attached to theopposite side. The solder balls facilitate mounting the resultingpackaged device onto a PCB, or similar surface.

[0019] A person of ordinary skill in the art will appreciate that thedie 12 may be mounted face-up with the surface having the integratedcircuit and bond pads 14 facing away from the substrate 16, or face-downso the surface with the integrated circuit and bond pads 14 are facingthe substrate 16. The surface of the die 10 having the integratedcircuit typically has a protective layer of polyimide or SiON to preventthe integrated circuit from being damaged during the die singulatingprocess or the die attachment process. The orientation of the die 12with respect to the substrate 16 will be determined by factors such asthe method of bonding to the bond pads 14 or the encapsulation method.

[0020] The semiconductor die 12 is attached to the substrate 16 by aplurality of pieces of adhesive film 20 a-c. As will be described inmore detail below, the adhesive film may be formed from a compliantmaterial. As shown in FIG. 1, there are three pieces of adhesive film 20a-c extending substantially the length of the die 12. However, a personof ordinary skill the art will appreciate that two or more pieces ofadhesive film may be used to attach the die 12 to the substrate 16. Itwill also be appreciated that the configuration of the adhesive film isnot limited to only single strips extending the length of the die 12 andthe substrate 16. For example, each of the single strips may beseparated into multiple pieces arranged along the length of the die.Alternatively, the pieces of adhesive film 20 a-c may also be arrangedat right angles near the corners of the die 12, or oriented to extendacross the width of the die 12. Therefore, the number of pieces ofadhesive film used to attach the die 12 to the substrate 16, or theparticular orientation of the pieces of adhesive film should not limitthe scope of the present invention.

[0021] The package structure 10 also includes a number of additionalcomponents that have been omitted from FIG. 1 in the interests ofbrevity. For example, an encapsulation material that may fill the spaceremaining between the adhesive film 20 a-c, and substantially cover thedie 12 and the substrate 16, are not illustrated in FIG. 1. However,methods and materials used for completing the assembly of the packagestructure 10 are well known in the art, and will not be discussed indetail herein.

[0022] Shown in FIGS. 2A-B are alternative embodiments of the pieces ofadhesive film that may be used to attach the die 12 to the substrate 16.FIG. 2A illustrates a film 30 consisting of a single layer of elastomermaterial. No additional layers of adhesive are required for the film 30because the elastomer material is itself adhesive. The film 30 ispressure bonded to the substrate 16, and then the die 12 is pressurebonded to the film 30. The resulting structure is subjected to arelatively high temperature process to ensure that the die 12 is firmlyattached to the substrate 16. As will be explained in greater detailbelow, the use of multiple pieces of the film 30 to attach the die 12 tothe substrate 16 will reduce the stress at the bond wire joint caused bythe thermal expansion of the elastomer material.

[0023]FIG. 2B illustrates a film 40 that may also be used in embodimentsof the present invention. The film 40 includes two adhesive layers 42and 44, and a carrier layer 46. Unlike the elastomer post method, wherethe elastomer post is formed initially, and an adhesive is appliedsubsequently, the film 40 is applied to the substrate 16 as a singlefilm. The film 40 is adhered to the substrate 16, and the die 12 isadhered to the film 40 by pressure bonding. The resulting packagestructure is subsequently heated to firmly attach the die 12 to thesubstrate 16. Although the carrier layer 46 is shown in FIG. 2B asconsisting of a single layer, a person of ordinary skill in the art willappreciate that the carrier layer 46 may be formed from multiple layersif so desired.

[0024] Using either the film 30 or 40 as a means of die attachmentprovides benefits over the elastomer post method described above. Thefilm 30 or 40 is positioned on and pressure bonded to the substrate 16using conventional techniques. No additional curing steps or applicationof adhesives are necessary. Additionally, with regards to thecoplanarity of the die 12 and the substrate 16, the films 30 and 40 arenot as susceptible to the problems related to coplanarity as the methodof screen printing discrete elastomer posts onto the surface of thesubstrate 16. Consequently, assembly failures related to the coplanarityof the two surfaces may be reduced when multiple pieces of the film 30or 40 are used for die attachment.

[0025] Shown in FIGS. 3A-B are cross-sectional views of the packagestructure 10 of FIG. 1, and a conventional package structure 110 havingan elastomer pad 120 attaching the die 12 to the substrate 16. Thethermal expansion for the multiple pieces of adhesive film 20 a-c andthe elastomer pad 120 are both governed by the following equation:

Δl=αΔTl ₀

[0026] where Δl is the change in the length of the material, a is thecoefficient of thermal expansion (CTE) of the material, ΔT is the changein temperature, and l₀, is the original length of the material at roomtemperature. For the purposes of illustration, assume that the sameelastomer material is used for the elastomer pad 120 and the multiplepieces of adhesive film 20 a-c, and that both structures are subjectedto the same change in temperature. Consequently, the only differencebetween the change in length for the elastomer pad, Δl_(pad), and forthe multiple pieces of elastomer, Δl_(multiple), is the original lengthof the corresponding elastomer pad, l_(0, pad) and l_(0, multiple). Thel_(0, pad) is the width of the elastomer pad 120, and thel_(0, multiple) is the sum of the individual widths of pieces 20 a-c,l_(0, 20a), l_(0, 20b), and l_(0, 20c), respectively. As illustrated byFIGS. 2A-B, l_(0, pad)>l_(0, multiple), and therefore,Δl_(pad)>Δl_(multiple). Thus, any stress applied to the wire bond jointdue to the thermal expansion of the elastomer pad 120 may be reduced byusing multiple pieces of elastomer film 20 a-c.

[0027] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. For example, each of theembodiments described previously may be simultaneously performed onseveral substrates 16 connected in strip form to facilitate the massproduction of the packaged devices. The individual packaged devices maybe singulated following solder ball attachment. Accordingly, theinvention is not limited except as by the appended claims.

1. A semiconductor device package, comprising: a semiconductor diehaving a first surface on which an integrated circuit and at least oneelectrically conductive bond pad are fabricated; at least oneelectrically conductive external terminal; an interposer having a dieattach surface and an external surface opposite of the die attachsurface disposed in between the semiconductor die and the at least oneexternal terminal, the interposer having at least one electricallyconductive interconnect electrically coupling the at least one bond padof the semiconductor die positioned adjacent to the die attach surfaceto the at least external terminal positioned adjacent to the externalsurface; and a plurality of pieces of adhesive film disposed in betweenthe semiconductor die and the interposer to adhere the semiconductor dieto the die attach surface of the interposer.
 2. The package of claim 1,further comprising an encapsulating material substantially fillingregions remaining in between the semiconductor die and the interposer.3. The package of claim 1 wherein the interposer comprises a flexiblematerial.
 4. The package of claim 1 wherein the plurality of pieces ofadhesive material comprises a compliant material.
 5. The package ofclaim 1 wherein each of the plurality of pieces of adhesive filmcomprises: a first adhesive layer adhered to the die attach surface ofthe interposer; a second adhesive layer adhered to the semiconductordie; and at least one carrier layer disposed in between the first andsecond adhesive layers and to which the first and second adhesive layersare adhered.
 6. The package of claim 1 wherein each of the plurality ofpieces of adhesive film comprises a single layer of elastomer material.7. The package of claim 1 wherein the first surface of the semiconductordie is adhered to the die attach surface of the interposer by theplurality of pieces of adhesive film.
 8. The package of claim 1 whereinthe at least one electrically conductive external terminal comprises asolder ball.
 9. The package of claim 1 wherein the plurality of piecesof adhesive film comprise strips of adhesive film positioned in parallelalong a longitude of the semiconductor die.
 10. The package of claim 1wherein a first and a second of the plurality of pieces of adhesive filmare positioned at a right angle with respect to each other.
 11. A devicepackage assembly for a semiconductor die being constructed from aprocess comprising: laminating a plurality of pieces of adhesive film toan interposer having at least one electrically conductive interconnect,the interposer further having a die attach surface to which thesemiconductor die is attached, and an external surface opposite of thedie attach surface; attaching to the interposer the semiconductor diehaving a first surface on which an integrated circuit and at least oneelectrically conductive bond pad are fabricated; and bonding the atleast one electrically conductive interconnect to the at least oneelectrically conductive bond pad.
 12. The package assembly of claim 11wherein the process further comprises substantially filling regionsremaining in between the semiconductor die and the interposer with anencapsulating material.
 13. The package assembly of claim 11 wherein theprocess further comprises attaching an external terminal to the at leastone electrically conductive interconnect adjacent to the externalsurface of the interposer.
 14. The package assembly of claim 13 whereinthe external terminal comprises a solder ball.
 15. The package assemblyof claim 11 wherein the interposer comprises a flexible material. 16.The package assembly of claim 11 wherein each of the plurality of piecesof adhesive film comprises a compliant material.
 17. The packageassembly of claim 11 wherein each of the plurality of pieces of adhesivefilm comprises a single layer of elastomer material.
 18. The packageassembly of claim 11 wherein the plurality of pieces of adhesive filmcomprise strips of film positioned in parallel along a longitude of thesemiconductor die.
 19. A method for reducing thermal mismatch stress ina semiconductor device package for a semiconductor die having anintegrated circuit and at least one electrically conductive bond pad,the method comprising adhering the semiconductor die to a die attachsurface of an interposer by using a plurality of pieces of adhesive filmdisposed therebetween, the interposer having at least one conductiveinterconnect electrically coupled to the bond pad, and farther having anexternal surface opposite of the die attach surface and to which anexternal terminal electrically coupled to the conductive interconnect isadjacent.
 20. The method of claim 19, further comprising substantiallyfilling regions remaining in between the semiconductor die and theinterposer with an encapsulating material and covering the at least oneconductive interconnect.
 21. The method of claim 19 wherein theinterposer comprises a flexible material.
 22. The method of claim 19wherein each of the plurality of pieces of adhesive film comprises acompliant material.
 23. The method of claim 19 wherein each of theplurality of pieces of adhesive film comprises: a first adhesive layeradhered to the die attach surface of the interposer; a second adhesivelayer adhered to the semiconductor die; and at least one carrier layerdisposed in between the first and second adhesive layers.
 24. The methodof claim 19 wherein each of the plurality of pieces of adhesive filmcomprises a single layer of elastomer.
 25. The method of claim 19wherein the external terminal comprises a solder ball.
 26. A method forpackaging a semiconductor device, comprising: laminating a plurality ofpieces of compliant adhesive film to an interposer having at least oneelectrically conductive interconnect, the interposer further having adie attach surface to which a semiconductor die is attached, and anexternal surface opposite of the die attach surface; attaching to theinterposer the semiconductor die having a first surface on which anintegrated circuit and at least one electrically conductive bond pad arefabricated; and bonding the at least one electrically conductiveinterconnect to the at least one electrically conductive bond pad. 27.The method of claim 26, further comprising substantially filling regionsremaining in between the semiconductor die and the interposer with anencapsulating material and covering the at least one conductiveinterconnect.
 28. The method of claim 26 wherein the interposercomprises a flexible material.
 29. The method of claim 26 wherein eachof the plurality of pieces of compliant adhesive film comprises: a firstadhesive layer adhered to the die attach surface of the interposer; asecond adhesive layer adhered to the semiconductor die; and at least onecarrier layer disposed in between the first and second adhesive layers.30. The method of claim 26 wherein each of the plurality of pieces ofcompliant adhesive film comprises a single layer of elastomer.
 31. Themethod of claim 26, further comprising attaching a solder ball to the atleast one electrically conductive interconnect adjacent to the externalsurface of the interposer.
 32. A method for packaging a semiconductordevice, comprising: laminating a plurality of pieces of compliantadhesive film to a semiconductor die having a first surface on which anintegrated circuit and at least one electrically conductive bond pad arefabricated; attaching to the semiconductor die an interposer having atleast one electrically conductive interconnect, the interposer furtherhaving a die attach surface to which a semiconductor die is attached,and an external surface opposite of the die attach surface; and bondingthe at least one electrically conductive interconnect to the at leastone electrically conductive bond pad.
 33. The method of claim 32,further comprising substantially filling regions remaining in betweenthe semiconductor die and the interposer with an encapsulating materialand covering the at least one conductive interconnect.
 34. The method ofclaim 32 wherein the interposer comprises a flexible material.
 35. Themethod of claim 32 wherein each of the plurality of pieces of compliantadhesive film comprises: a first adhesive layer adhered to the dieattach surface of the interposer; a second adhesive layer adhered to thesemiconductor die; and at least one carrier layer disposed in betweenthe first and second adhesive layers.
 36. The method of claim 32 whereineach of the plurality of pieces of compliant adhesive film comprises asingle layer of elastomer.
 37. The method of claim 32, her comprisingattaching a solder ball to the at least one electrically conductiveinterconnect adjacent to the external surface of the interposer.